1. Field of the Invention
This invention relates generally to the production of integrated circuits, and more particularly to processes for making contacts and interconnections among integrated circuit devices.
2. Description of the Prior Art In the prior art, individual integrated circuit devices, such as MOSFETs, are typically interconnected by the method illustrated in FIGS. 1A, 1B, and 1C. First, the MOSFETs are fabricated on a semiconductor substrate by methods well known to those skilled in the art to form the structure illustrated in FIG. 1A. Next, as seen in FIG. 1B, a passivation layer, such as phosphosilicate glass, is uniformly deposited over the MOSFETs, and contact holes are etched through the passivation layer over the sources and drains of the MOSFETs. As illustrated by FIG. 1C, a metal layer of, for example, an aluminum alloy is then deposited over the passivation layer to create contacts to the sources and drains of the MOSFETs through the contact holes.
Finally, the metal layer is patterned to correctly interconnect the various MOSFETs of the integrated circuit.
Although this prior art method is generally adequate, it becomes less so as devices are scaled down and become progressively smaller. For example, the prior art method shown in FIGS. 1A-1C is subject to lithographic misalignment and to undercutting during contact etch. In consequence, MOSFET devices require spacing between their source/drain contact holes and the edges of the polysilicon gate and field oxide. This additional spacing requirement results in wasted areas in the integrated circuit and in increased junction capacitances, and limits the density the integrated circuit. Furthermore, the spacing between a contact hole and the edge of the active device increases the contact resistance and, consequently, further degrades device performance.
Several approaches have been proposed to overcome the problems of the prior art. With MOSFET devices, one approach is to use a polysilicon layer to contact the source and drain regions in order to minimize the junction area. This approach is represented in FIG. 2. Connections between the polysilicon layer and the metal layer are then formed on the field oxide layer. The major drawback to this approach is that during the polysilicon etch, the silicon substrate is also etched inadvertently. The effective junction depth can therefore be affected and the substrate may also be damaged. Another drawback of the method illustrated in FIG. 2 is that the polysilicon layer is not a particularly good conductor and thus creates considerable resistance between the metal contacts and the source or drain regions.
The approach illustrated in FIG. 3 addresses the contact resistance problem. To reduce resistance, a refractory metal, such as titanium, can be uniformly deposited over the polysilicon and subsequently annealed to form low-resistivity silicide, and the unreacted refractory metal subsequently removed. Unfortunately, the method illustrated by the structure shown in FIG. 3 can still damage the silicon substrate during the etching of the polysilicon layer. Furthermore, since a polysilicon layer is used to contact the source and drain of the MOSFET, the method of FIG. 3 can only be used if the polysilicon is closely matched in crystal structure, polarity, and doping level to the source and drain. If the polysilicon is not closely matched, large contact resistances and parasitic diode effects can be created, possibly damaging the operation of the device.
Some attempts have been made in the prior art to use silicide as an ohmic contact. For example, Ku in the "IBM Technical Disclosure Bulletin", Vol. 22, No. 4 (September, 1979) discloses ohmic contacts for small, shallow structure devices which are made by applying a metal layer over a dielectric film, applying a polysilicon layer over the metal layer, patterning the polysilicon, and converting the patterned polysilicon to silicide by reacting it with the underlying metal layer.
A problem of Ku's method is the difficulty in forming a polysilicon layer over a metal layer. If the two layers are formed by a Low-Pressure Chemical Vapor Deposition (LPCVD) method, the LPCVD machine must be pumped down twice, i.e., once for the metal deposition, and once for the high temperature polysilicon deposition.
Furthermore, Ku does not address the problem of connecting the silicide layer to a silicon layer. Ku's silicide is formed totally over a metal layer which, in turn, is formed totally over a dielectric layer. In fact, the problem of connecting a silicide layer to a silicon layer is not well addressed in the prior art as a whole. The current state of the art only allows the connection of n-type polysilicon based silicide to n-type silicon without the aforementioned problems of high ohmic contacts and parasitic diode effects. Obviously, such silicide to silicon connects are inadequate in a p-channel MOS or CMOS environment.